1. Field of the Invention
The present invention relates to a method for forming ohmic contact between a semiconductor substrate and electrode wiring.
2. Description of the Related Art
For example, ohmic contact between a semiconductor substrate and electrode wiring has a structure as shown in FIGS. 1a and 1b. The ohmic contact shown in FIGS. 1a and 1b is formed by the following procedures. First, a partially thick oxide film 3 is formed on a p-type semiconductor (Si) substrate 1 by a thermal oxidizing method using a predetermined mask. For example, this oxide film 3 is formed by an SiO.sub.2 film having a thickness of 1.0 .mu.m. After the above mask is then removed, a thin oxide film 2 is formed in a masked portion. For example, this oxide film 2 is constructed by an SiO.sub.2 film having a thickness from 0.03 to 0.10 .mu.m. This oxide film 2 is set to a gate oxide film. Next, a polycrystal silicon film or a thin film of a high melting point metal is formed by a CVD method or a sputtering method such that this film has a thickness from 1.0 to 1.5 .mu.m. Next, required portions are left and the other portions are removed with this metallic thin film as a gate electrode portion and wiring. Next, phosphorus (P) or arsenic (As) acting as n-type impurities is implanted by a thermal diffusive method or an ion implanting method with the gate electrode portion 2 and the thick oxide film 3 as masks. Thus, a source region, a drain region and an n.sup.+ wiring region 2 are formed on a substrate surface. Next, a PSG film 4 is formed on an entire upper face of the substrate by the CVD method. The PSG film 4 is made of mixing glass of SiO.sub.2 --P.sub.2 O.sub.5. Next, a contact hole 6 as an opening is formed in the PSG film 4. The substrate upper face is then covered with a metallic thin film 5 having aluminum as a principal component. Thereafter, the metallic thin film 5 is selectively removed from the substrate upper face so that electrode wiring coming in contact with the n.sup.+ region of the substrate is formed.
As shown in FIGS. 1a and 1b, the contact hole 6 is surrounded by the n.sup.+ layer 2 with a predetermined margin. Therefore, a wiring region formed by the n.sup.+ layer 2 has an area wider than the contact hole 6. Further, a wiring interval of adjacent separate n.sup.+ layers is also determined in accordance with a size of this contact hole. It is considered to improve an integration degree of an electric circuit that a size of the wiring region formed by the n.sup.+ layer 2 is reduced and the size of the contact hole 6 is approximately equal to or slightly greater than that of the n.sup.+ layer 2. However, in this case, the oxide film 3 is also etched together with the PSG film 4 so that there is a danger of exposing the p-type semiconductor substrate 1. In particular, when a thin n.sup.+ layer is formed by the ion implanting method, the danger of exposing the p-type semiconductor substrate 1 by the above etching becomes very high. Further, there is a case in which the p-type semiconductor substrate is exposed to the contact hole even when the position of a mask pattern is slightly shifted at a time of photolithography for forming the contact hole. When electrode wiring is formed in a state in which the p-type semiconductor substrate 1 is exposed to the contact hole, the electrode wiring comes in contact with the p-type semiconductor substrate 1 as well as the desired n.sup.+ layer 2 so that a p/n junction is broken. As a result, the function of a formed integrated circuit itself is damaged.
For example, Japanese Patent Publication (KOKOKU) No. 61-38858 shows a manufacturing method of a semiconductor device for solving this problem. In this manufacturing method, a semiconductor in a contact hole portion of a source and a drain is exposed. Thereafter, ions are again implanted into the semiconductor so that exposure of a p-type semiconductor substrate is corrected. In accordance with this manufacturing method, it is possible to prevent the above p/n junction from being broken by a shift in mask pattern at the photolithographic time.
However, in the above manufacturing method of the semiconductor device, heat treatment is taken after the contact hole is opened. When an insulating film having a reflowing property is used, a shape of the contact hole is changed and deformed. Therefore, when the contact hole is small, there is a case in which the contact hole once opened is closed by the above deformation. Accordingly, there is a constant restriction on fining of the contact hole.